A Multicore Re-Configurable Processor Platform for Energy & Throughput Aware Platform
|Budget||PKR 27.16 million|
|Status||Project in Inclosure Process|
|Progress Report||View Progress Report|
The project developed a reconfiguration engine to control Cache Size/Associativity, Number of Processor Cores, and Operating Frequency as the control variables which are using the hardware performance counters for run-time application analysis and feeding the results to the reconfiguration engine to optimize the control variables. Through this project the team members gained hands- on-experience on porting a processor on FPGA board running Linux, and some standard multicore benchmarks such as NAS Parallel Benchmarks. Subsequently, the basic single core processor was also integrated with an adaptive cache memory with run-time reconfigurable line size and associativity.